(1) Field of the Invention
The present invention generally relates to level conversion circuits and more particularly to a level conversion circuit for converting ECL-level signals into MOS-level signals. Further, the present invention is concerned with an address signal decoding system of a memory device using such a level conversion circuit.
(2) Description of the Prior Art
FIG.1 is a block diagram of a RAM device comprised of Bi-CMOS (Bipolar-Complementary Metal Oxide Semiconductor) transistors. The RAM device shown in FIG.1 comprises a chip main body 1, address signal input terminals 2.sub.1 and 2.sub.2 respectively receiving ECL-level signals A1 and A2, an input buffer circuit 3, a level conversion circuit 4, an address decoder 5, a memory cell array 6, a sense amplifier 7 and an output terminal 8. The input buffer circuit 3 derives pairs of ECL-level complementary signals A1 and /A1 and A2 and /A2. It will be noted that A1 and A2 shown in FIG.1 are written as "/A1" and "/A2" in the specification for convenience.
The level conversion circuit 4 converts the ECL-level signals A1, /A1, A2 and /A2 into MOS-level signals a1, /a1, a2 and /a2, respectively. The address decoder 5 derives decode signals b1, b2, b3 and b4 from the MOS-level signals a1, /a1, a2 and /a2. The decode signals b1, b2, b3 and b4 are applied to the memory cell array 6, and data is written into or read out from a specified memory cell. The readout data is sensed by the sense amplifier 7 and output to the output terminal 8.
FIG.2 is a circuit diagram of the input buffer circuit 3 and the level conversion circuit 4. The input buffer circuit 3 is composed of two input buffer circuits 9.sub.1 and 9.sub.2 / The input buffer circuit 3 comprises power supply lines 10.sub.1 and 10.sub.2 set to a ground voltage of zero volt, power supply lines 11.sub.1 and 11.sub.2 set to -5.2 V, load resistors 12.sub.1, 12.sub.2, 13.sub.1 and 13.sub.2, npn transistors 14.sub.1, 14.sub.2, 15.sub.1 and 15.sub.2, constant-current sources 16.sub.1 and 16.sub.2, and reference voltage input terminals 17.sub.1 and 17.sub.2 to which identical reference voltages V.sub.R are respectively applied.
The level conversion circuit 4 is composed of two level conversion circuits 18.sub.1 and 18.sub.2, power supply lines 19.sub.1 and 19.sub.2 set to zero volt, power supply lines 20.sub.1 and 20.sub.2 set to -5 V, pMOS transistors 21.sub.1, 21.sub.2, 22.sub.1 and 22.sub.2, nMOS transistors 23.sub.1, 23.sub.2, 24.sub.1 and 24.sub.2, and output terminals 25.sub.1, 25.sub.2, 26.sub.1 and 26.sub.2.
When the address signal A1 applied to the input buffer circuit 91 is maintained at a low (L) level, the NPN transistors 14.sub.1 and 15.sub.1 are turned OFF and ON, respectively. Then, the levels of nodes 27 and 28 are switched to a high (H) level (=0 V) and a low (L) level (=-1.6 V). Hence, the pMOS transistors 21.sub.1 and 22.sub.1 of the level conversion circuit 18.sub.1 are turned ON and OFF, respectively, and the nMOS transistors 23.sub.1 and 24.sub.1 are turned OFF and ON, respectively. Thus, the levels of the output terminals 25.sub.1 and 26.sub.1 switch to a high (H) level (=0 V) and a low level (=-5 V), respectively.
When the address signal A1 is at H, the NPN transistors 14.sub.1 and 15.sub.1 are turned ON and OFF, respectively, and the levels of the nodes 27 and 28 are switched to L(=-1.6 V) and H(=0 V), respectively. Hence, the pMOS transistors 21.sub.1 and 22.sub.1 of the level conversion circuit 181 are turned OFF and ON, and the nMOS transistors 23.sub.1 and 24.sub.1 are turned ON and OFF, respectively. As a result, the levels of the output terminals 25.sub.1 and 26.sub.1 are switched to L (=-5 V) and H(=O V), respectively. The input buffer circuit 9.sub.2 and the level conversion circuit 18.sub.2 operate in the same manner as describe above.
In some cases, emitter follower circuits are inserted between the input buffer circuit 3 and the level conversion circuit 4. In this configuration, the high level of each address signal is equal to -0.8 V.
However, the conventional RAMs having Bi-MOS circuits as described above have the following disadvantages. As shown in FIG.3, a wired-OR circuit (composed of bipolar transistors) 29 is connected to the output terminals of the input buffer circuit 3 in order to increase the operation speed of the RAM. The wired-OR circuit 29 decodes the address signals A1 and A2 and generates ECL-level decode signals B1-B4, which are converted into the MOS-level decode signals b1-b4 by a level conversion circuit 30. However, the level conversion circuit 30 cannot be formed with the conventional level conversion circuit 4 shown in FIG.1, because the level conversion circuit 4 needs complementary input signals.